In multiprocessor computing environments and other complex computing systems, high frequency, high throughput data communication buses are necessary to avoid latencies incurred in moving data among components of a computing system, such as processors, memories, and other peripheral devices. Many modern systems use high speed serial communication channels as system buses to transmit data among the components of the system.
One such high speed serial communication channel is a PCI Express system bus. PCI Express system buses require a PCI Express compatible interface associated with each component to which the bus connects. The interface sends and receives data from the system components connected to the PCI Express bus. To do so, the interface must send and receive transaction packets on the bus and manage the parallelization/serialization of that data. The interface must also determine the type of transaction to be performed using header information contained in the received data, or must prepare transaction packets for other systems/interfaces to decode.
Many serial interfaces implement a single finite state machine controller which, using the header information, distributes commands based on the transaction to be performed based on the transaction packet. Such serial interfaces generally receive a serial transaction packet in its entirety, then process the header information contained in the packet and manage the data in the packet according to the decoded header information. The header decoding and/or data management can consume a number of system clock cycles to accomplish in the finite state machine controller, which can cause delay in processing the transaction packet.
An example operational flow of an existing serial interface state machine controller is illustrated in FIGS. 1 and 2. In such an existing system, header receipt, data receipt, data processing, and data management steps occur sequentially, introducing latency into the system based on the processing time for the interface to decode the header and generate data routing signals.
Certain serial bus protocols do not prohibit sending or receiving a transaction on each bus clock cycle. For example, a PCI Express system bus may operate using a two nanosecond clock cycle, and may hold a separate transaction on each clock cycle. Systems using a slow-processing finite state machine controller may not be able to support such line speed bus activity. This is because certain transactions can take more than one bus clock cycle to decode the header information and appropriately route the data in the transaction packet. In these cases, latency may need to be introduced into the system, such as by storing and delaying processing of an inbound transaction packet, or by introducing an idle character onto the bus. Adding latency to the system bus lowers the maximum throughput, or bandwidth, at the interface.
For these and other reasons, improvements are desired.